The present invention relates to the field of redundancy management of aircraft critical control architectures. More particularly, the present invention relates to multiple layer cross processor error detection for redundant aircraft critical control architectures. Still more particularly, the present invention relates to processor survivorship for a redundant aircraft critical control computer architecture implemented with multiple layer cross processor control command processing error detection.
Flight control systems are constrained by Federal Air Regulations to provide safe control of an aircraft throughout the regimes in which the flight control system is utilized. Any failure condition, which prevents continued safe flight and landing, must be extremely improbable. Present regulations require a very low probability of failure per hour for flight critical components. A flight critical portion of a flight control system is one of these critical components, the failure of which endangers the lives of the persons aboard the aircraft. Generally, the safety levels of components of the system is determined by aircraft level analysis, known to those skilled in the art. Analyses of non-critical flight control system elements, however, typically are performed to a much lesser probability level of failures per hour than flight critical portions. For example, components of a flight control system utilized in landing aircraft may be designated as flight critical, whereas, certain components utilized during cruise control may be designated as non-critical.
Flight control systems utilizing analog computers and components had been prevalent in the art wherein it had become completely practical to perform the verification and validation procedures to certify conformance of such systems to the safety requirements of the Federal Air Regulations. A known technique for enhancing the reliability and fault tolerance of flight critical components is that of dual redundancy. Dual redundancy is the utilization of two identical channels monitoring to detect a failure in one of the channels. Although such systems are effective against random faults, cross channel monitoring does not provide effective detection of generic faults. A generic fault is defined as a fault that is inadvertently designed into a component such that all like components generically have this fault and respond in like but defective manners. When identical components having a generic fault are in respective redundant channels, the cross channel monitoring compares the same, although erroneous output from both channels, and therefore does not detect the error.
Such prior art dual redundant systems with identical channels provided fail passive performance with respect to random faults. When the cross-channel monitoring detects different outputs from the two channels, the dual channel flight control system is disengaged thereby failing in a passive manner. In order to effect fail operational performance with respect to random faults, two such dual redundant channel pairs were conventionally utilized whereby a miscomparison in one pair would result in shut down of that pair with the other channel pair remaining in operation. The occurrence of a second random fault in a remaining channel pair would affect passive shutdown of the system. For the reasons discussed above, such multiple redundant systems were ineffective in detecting generic faults.
In order to overcome these problems, the automatic flight control technology has advanced to the concept of dissimilar redundancy. In dissimilar redundancy, dual dissimilar processors perform identical tasks utilizing dissimilar software with cross channel monitoring to detect failures. With this approach, generic errors designed into the processor or software of one channel will not exist in the processor or software of the other channel and the cross channel monitoring will detect the discrepancy. Such prior art dual dissimilar processor systems would be fail passive with respect to both random and generic faults. A random or generic fault occurring with respect to one of the dissimilar processors would be detected by the cross channel monitoring and the dual dissimilar processor system passively disengaged.
None of the related art system configurations mentioned above provide fail operational performance with respect to generic faults. Utilization of multiple dual redundant systems with similar processing elements fails to detect generic faults for the reasons discussed above. A mirror replication of dual channel subsystems utilizing dissimilar processing elements would result in a fail passive capability rather than a fail operational performance. This is because a generic fault detected in one dual subsystem causing that subsystem to be disengaged would be present in corresponding element in any other subsystem, also resulting in disengagement thereof. Thus, this dual dissimilar configuration instead of providing fail operational performance results in a fail passive system that is the property otherwise obtained from one half of the system.
U.S. Pat. No. 4,622,667 issued to Yount and entitled xe2x80x9cDigital Fail Operational Automatic Flight Control System Utilizing Redundant Dissimilar Data Processingxe2x80x9d describes an arrangement which provides fail operational performance for a first random or generic failure and fail passive performance for a second random or generic failure. An alternative embodiment in Yount provides fail operational performance for the first two random failures and fail passive performance for a third random failure and provides fail operational performance for the first generic failure and fail passive performance for the second generic failure.
The fail operational arrangement of Yount utilizes at least two independent flight control channels, each composed of two lanes. Each lane is comprised of independent I/O. One lane in each channel includes a first digital data processor and the other lane includes a second data digital processor with an active third processor. The two lanes in each channel are cross-monitored to detect disagreements between the outputs of the first and second processors and the outputs of the first and third processors. All the processors perform the same system tasks with respect to flight critical functions. The three processors in each channel provide dissimilar data processing with respect to each other. The two processors that do not have active third processors associated therewith in the respective subsystems provide dissimilar data processing with respect to each other.
The six processors of the two channels in Yount are arranged so that there are only three types of dissimilar data processing. When the cross monitoring in a channel detects a discrepancy between the outputs of the first and second processors, the output of the second processor is disabled and the active third processor continues servicing its channel. If the cross monitoring in a channel detects a discrepancy between the outputs to the first and second processors, the entire channel is disengaged. In effect, the third processor of the channel is substituted for the second processor when the second processor is detected to be defective, and if the substitution does not resolve the discrepancy, the channel is disengaged. In the alternative embodiment, the arrangement is fail operational for the first two random failures and fail passive for a third random failure and which is fail operational for the first generic failure and fail passive for the second generic failure, the arrangement utilizes three channels in a somewhat similar manner.
In another flight critical computer architecture, and internal monitoring mechanism of the MD-11 Flight Control Computer having a dual lane computer channel with two processors per lane is apparent. The MD-11 Flight Control Computer is a dual lane computer with two processors in the first lane and two processors in a second lane. With the MD-11 Flight Control Computer, one of the processors in one lane, is locked out so that it is unable to output flight critical commands. No comparison monitoring is performed with the locked out processor so the MD-11 configuration is redundant in only one lane, i.e. the second lane. Therefore, each MD-11 flight critical computer incorporates a fail passive design since a single processor fault in the non redundant lane can shut down the flight control computer.
A single channel fail operational flight critical computer system for aircraft is described in U.S. Pat. No. 5,550,736 issued to Hay et al (xe2x80x9cHayxe2x80x9d). The Hay patent describes a flight critical computer system based on dual independent computing lanes with a primary and a redundant processor in each lane. Each dual independent computing lane produces command signals generated by the primary and the redundant processors. Three independent monitors are provided to monitor the command signals produced by the first primary and the second primary, the second primary and the first redundant, and the first primary and the second redundant, respectively. Selection logic completes the system and selects from the first, second and third comparison signals at least one of the output signals generated by the processors as a command signal of the system. This permits at least one processor to fail before both command signals from the lanes, respectively, are disabled.
The related art inventions heretofore described are all useful to provide fault tolerant flight critical computer architectures. However, past precedent also suggests the need for clear physical separation between redundant computing lanes. Therefore, a need exists for aircraft critical control computer modular architecture that provides segregated independent processing units. Moreover, a further need exists for a aircraft critical control computer modular architecture that provides fail-operational or at least fail-passive performance.
It is an object of the present invention to provide a redundant aircraft critical control modular architecture featuring cross processor error detection and fail operational processor survivorship.